1. Field of the Invention
The present invention relates to a technical field of level shifter and, more particularly, to a level shifter for low to high voltage conversion.
2. Description of Related Art
Most level shifters are applied for voltage conversion, such as a control signal conversion from low voltage to high. Due to few required electronic devices and easier implementation, a level shifter is widely applied in scan drivers of computer systems and flat displays.
FIG. 1 is a schematic diagram of a typical level shifter. In FIG. 1, the typical level shifter consists of an input-stage level shifter 11, a first output circuit 12 and a second output circuit 13. The level shifter 11 consists of high-voltage devices including PMOSs 111, 112 and NMOSs 113, 114, and an inverter 115 driven by a low-level voltage source VDD. The first output circuit 12 consists of PMOS 121 and NMOS 122. The second output circuit 13 consists of PMOS 131 and NMOS 132.
As shown in FIG. 1, the input-stage level shifter 11 uses an input signal A (at a low-level voltage source VDD of which can provide a low voltage of 0V and a high voltage range of 2.3˜2.5V) to control PMOSs 111, 112 and NMOSs 113, 114 for outputting a high-level voltage signal VPP (normally at 3.3 V) through the first and second output circuits 12 and 13. Signals outputted by the circuits 12 and 13 have opposite phases.
When an input signal A of 2.5V is entered to the input of the inverter 115, a gate of NMOS 113 receives a control signal of 0V and a gate of NMOS 114 receives a control signal of 2.5V. Thus, NMOS 113 is turned off and NMOS 114 is turned on. Next, PMOS 111 is turned on, PMOS 112 is turned off, PMOS 121 is turned on, and NMOS 122 is turned off. Accordingly, point B outputs a 3.3V VPP signal as a high-level control signal. In addition, PMOS 131 is turned off and NMOS 132 is turned on, so PMOS 131 is turned off and NMOS 132 is turned on. Point C outputs a 0V high-level control signal.
Similarly, when the input signal A is a 0V control signal, NMOS 113 is turned on, NMOS 114 is turned off, PMOS 111 is turned off, PMOS 112 is turned on, PMOS 121 is turned off, and NMOS 122 is turned on, so that point B outputs a 0V high-level control signal. In addition, PMOS 131 is turned on and NMOS 132 is turned off, so that point C outputs another high-level control signal with 3.3V VPP.
However, the above circuit encounters problems. Since current ICs are usually formed by advanced processes, low-level voltage source VDD becomes lower and lower (for example, as low as 1˜1.5V). Thus, a lower voltage source VDD may not turn on the threshold voltage of a high-voltage NMOS device (such as 113 and 114 of FIG. 1). That is, a low-level voltage source cannot turn on a high-voltage device as it provides a voltage smaller than a threshold voltage of the high-voltage device. Therefore, the entire level shifter cannot work. In addition, when a high voltage of the low-level voltage source VDD is too low (1˜1.5V), which is slightly higher than the threshold voltage of the high-voltage device, an output signal of the voltage source VDD has unbalanced rising/falling waveforms and thus the level shifter has longer transition time.
Therefore, it is desirable to provide an improved level shifter to mitigate and/or obviate the aforementioned problems.